Welcome to the IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE) page! This site aims to provide links and hints to get you started using open-source IC design tools, especially if you want to participate in the SSCS PICO Chipathon or the Code-a-Chip Travel Grant competition.

General Information About Open-Source IC Design

Open-source IC design tools have come a long way in recent years. While the start can be confusing, plenty of information is available online.

To start, please look at Matt Venn’s collection of Awesome open-source ASIC resources. This GitHub page collects many links to several tools and information sites. Generally, it is good to get a GitHub account since many of the relevant SW packages are hosted there.

In addition to GitHub, YouTube is a treasure trove of helpful information. Many users have published tutorials; sometimes, the lead developers of essential tools publish How-To videos themselves. Once you know what to look for, you can find it. Hint: Search for a specific tool you want to learn.

Since the individual open-source SW packages evolve quickly, documentation is often lacking behind. Luckily, the open-source developer community is accessible, and you can often reach them directly on Slack to help you out. You should request access to the opensource-silicon Slack space as this is the watering hole where everyone meets. There is also a dedicated channel for the 2023 Chipathon (#ieee-sscs-dc-23).

And finally: Visit our IEEE SSCS page for all kinds of information related to solid-state circuits, like tutorials, conferences, publications, etc.

Open-Source PDKs

Open-source IC design tools would not work without documentation, simulation models, pre-made digital cells, and runset files. These collaterals are usually called a Process Development Kit (PDK), and luckily, there exist open-source PDKs from multiple wafer foundries.

SkyWater Technology SKY130

Usually, PDKs are only shared under strict non-disclosure agreements (NDA), but not in this PDK from SkyWater Technology. In this location (and also here on GitHub), you can find a host of helpful information about this available 130nm CMOS process.

While this process is a mature node (and a far cry from a leading nm-FinFET node), it has a rich list of process options and features, which is more than sufficient for many analog and digital designs, and even RF up to a few GHz:

  • Support for internal 1.8V with 5.0V I/Os (operable at 2.5V)
  • 1 level of local interconnect
  • 5 levels of metal (inductor-capable)
  • A high sheet-rho polysilicon resistor
  • Optional (dual) MiM capacitors
  • HV extended-drain NMOS and PMOS up to 20V

Here is an excellent device overview of this technology. There is also a rich set of digital standard cells available.

In this sheet, you can find a summary of the various mask (GDS) layers, wiring resistance and capacitance, and electromigration rules.

Global Foundries GF180MCU

Another example of an open-source PDK is from Global Foundries. This 180nm CMOS process is documented here and here, and provides the following features:

  • Support for 3.3V/5V/6V MOSFET (minimum length of 280nm)
  • Optional High sheet-rho polysilicon resistors
  • Optional MIM capacitor
  • Different metallization options (from 2 up to 6 metal layers, with optional thick-metal)

The different available devices in this technology can be found here, and the metallization schemes are described here. There are also digital standard cells and memories available. A pad library is also offered.

Digital IC Design

Digital circuit design in the modern era uses a flow, usually starting with a high-level behavioral description. The main two hardware description languages (HDL) used nowadays are Verilog and VHDL. We propose to use Verilog, as the support in the open-source tools is generally a bit better.

Once you are happy with your behavioral model, a suite of tools takes you from Verilog to GDS (the geometric mask data file format you send for production to a foundry). This methodology is called RTL2GDS, and OpenLane is the flow we propose to use.

Find more information on approaching a digital design see here.

If you consider Verilog and VHDL old-school (we don’t), there is a rich host of advanced methodologies collected by Andreas Olofsson to get you started.

Analog IC Design

Despite highly automated digital circuit design, analog circuit design is still relatively old school. While there are many attempts to automate various steps like device sizing or layout construction, especially for beginners, we propose to use a classical flow: The analog circuits are hand-drawn in a schematic editor, simulated in a SPICE-class simulator, and finally, the IC layout is manually drawn.

If you think analog design is the right thing for you (and hopefully it is!), you can find more information here.

Open-Source IC Design Tools

As stated in the general introduction section, many open-source tools are available. This variety can be overwhelming initially, and sometimes a local installation on a Linux machine is not straightforward. A few developers try to flatten the learning curve by providing pre-built tool collections. One example is the IIC-OSIC-TOOLS collection from Johannes Kepler University, prepared as a virtual machine (VM) using Docker. This VM has plenty of tools installed (as documented in this README file), as well as pre-installed SKY130 and GF180MCU PDKs.

For GF180MCU there are these installation How-Tos available for a local installation on a Linux machine: the first for a digital implementation flow, and the second for an analog design flow.

How to Tape Out an IC

Preparing an IC layout for production in a wafer foundry is a lengthy process described at a high level on this page.

IEEE SSCS Educational Resources

IEEE SSCS Youtube Channel (circuit insights and various short courses):

IEEE SSCS Resource Center (extensive archive, free for SSCS members):



Contact Harald Pretl at h dot pretl at ieee dot org.

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