IC Tapeout Procedure

Preparing an IC layout for production in a wafer foundry is a lengthy process. It usually involves quite a few checks, and once all are passed, and the IC layout is complete with pads, seal ring, etc., then the resulting layout database is sent to the foundry, usually in the form of a GDS2 or OASIS file.

In the Chipathon we are using the service of efabless.com. They have prepared an infrastructure chip including pads, ESD, programming infrastructure, and so on, called Caravel (for digital IC) or Caravel Analog (for analog IC). In this document, you can find some preliminary documentation on how to prepare your design using these infrastructure chips for TO at efabless.com.

Since IC fabrication is costly (tens of thousands of dollars reaching into millions depending on process node) and time-consuming (the turn-around time from submitting design data to receiving a prototype is a few months) it is of utmost importance to make sure that the implemented design is error-free. One way to ensure this (besides extensive simulation on all levels of the design hierarchy) is to have a formal design review before the tape-out, where several engineers review the design, layout, simulation results, etc. In this TO checklist, a few important considerations are collected.